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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg726/ADG732 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 16-/32-channel, 4 +1.8 v to +5.5 v, 2.5 v analog multiplexers features 1.8 v to 5.5 v single supply 2.5 v dual-supply operation 4 on resistance 0.5 on resistance flatness 48-lead tqfp or 48-lead 7 mm 7 mm csp packages rail-to-rail operation 30 ns switching times single 32-to-1 channel multiplexer dual/differential 16-to-1 channel multiplexer ttl/cmos compatible inputs for functionally equivalent devices with serial interface see adg725/adg731 applications optical applications data acquisition systems communication systems relay replacement audio and video switching battery-powered systems medical instrumentation automatic test equipment functional block diagrams ADG732 en s1 s32 wr cs a4 a3 a2 a1 a0 d 1-of-32 decoder s1a s16a da adg726 en wr a3 a2 a1 a0 s1b s16b db 1-of-16 decoder csa csb product highlights 1. +1.8 v to +5.5 v single- or 2.5 v dual-supply operation. these parts are specified and guaranteed with +5 v 10%, +3 v 10% single-supply, and 2.5 v 10% dual- supply rails. 2. on resistance of 4 ? 3. guaranteed break-before-make switching action 4. 7 mm 7 mm 48-lead chip scale package (csp) or 48-lead tqfp package general description the adg726/ADG732 are monolithic cmos 32-channel/dual 16-channel analog multiplexers. the ADG732 switches one of 32 inputs (s1-s32) to a common output, d, as determined by the 5-bit binary address lines a0, a1, a2, a3, and a4. the adg726 switches one of 16 inputs as determined by the 4-bit binary address lines a0, a1, a2, and a3. on-chip latches facilitate microprocessor interfacing. the adg726 device may also be configured for differential opera- tion by tying csa and csb together. an en input is used to enable or disable the devices. when disabled, all channels are switched off. these multiplexers are designed on an enhanced submicron process that provides low power dissipation yet gives high switching speed, very low on resistance, and leakage currents. they operate from a single supply of +1.8 v to +5.5 v and a 2.5 v dual supply, making them ideally suited to a variety of applications. on resistance is in the region of a few ohms and is closely matched between switches and very flat over the full signal range. t hese parts can operate equally well as either multiplexers or demultiplexers and have an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. all channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. they are available in either 48-lead csp or tqfp packages.
rev. 0 e2e adg726/ADG732especifications 1 (v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.) b version e40 c parameter +25 c to +85 cu nit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )4 typ v s = 0 v to v dd , i ds = 10 ma; 5.5 6 max test circuit 1 on resistance match between 0.3 typ v s = 0 v to v dd , i ds = 10 ma channels ( r on ) 0.8 max on resistance flatness (r flat(on) ) 0.5 typ v s = 0 v to v dd , i ds = 10 ma 1 max leakage currents v dd = 5.5 v source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.25 1 na max test circuit 2 drain off leakage i d (off) 0.05 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; adg726 0.5 2.5 na max test circuit 3 ADG732 1 5 na max channel on leakage i d , i s (on) 0.05 na typ v d = v s = 1 v, or 4.5 v; adg726 0.5 2.5 na max test circuit 4 ADG732 1 5 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.5 a max c in , digital input capacitance 5 pf typ dynamic characteristics 2 t transition 23 ns typ r l = 300 , c l = 35 pf, test circuit 5 34 40 ns max v s1 = 3 v/0 v, v s32 = 0 v/3 v break-before-make time delay, t d 18 ns typ r l = 300 , c l = 35 pf; 1 ns min v s = 3 v; test circuit 6 t on ( cs , wr )18 ns typ v s = 3 v; test circuit 7 25 32 ns max r l = 300 , c l = 35 pf; t off ( cs , wr )17 ns typ v s = 3 v; test circuit 7 23 29 ns max r l = 300 , c l = 35 pf; t on ( en )24 ns typ r l = 300 , c l = 35 pf; 32 40 ns max v s = 3 v; test circuit 8 t off ( en )16 ns typ r l = 300 , c l = 35 pf; 22 25 ns max v s = 3 v; test circuit 8 charge injection 5 pc typ v s = 2.5 v, r s = 0 , c l = 1 nf; test circuit 9 off isolation e72 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 10 channel-to-channel crosstalk e72 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 11 e3 db bandwidth r l = 50 , c l = 5 pf; test circuit 12 adg726 34 mhz typ ADG732 18 mhz typ c s (off) 13 pf typ f = 1 mhz c d (off) adg726 170 pf typ f = 1 mhz ADG732 340 pf typ f = 1 mhz c d , c s (on) adg726 175 pf typ f = 1 mhz ADG732 350 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 10 a typ digital inputs = 0 v or 5.5 v 20 a max notes 1 temperature range is as follows: b version: e40 c to +85 c. 2 guaranteed by design; not subject to production test. specifications subject to change without notice.
rev. 0 e3e adg726/ADG732 b version e40 c parameter +25 c to +85 cu nit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )7 typ v s = 0 v to v dd , i ds = 10 ma; 11 12 max test circuit 1 on resistance match between 0.35 typ v s = 0 v to v dd , i ds = 10 ma channels ( r on )1 max on resistance flatness (r flat(on) )3 typ v s = 0 v to v dd , i ds = 10 ma leakage currents v dd = 3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.25 1 na max test circuit 2 drain off leakage i d (off) 0.05 na max v s = 1 v/3 v, v d = 3 v/1 v; adg726 0.5 2.5 na max test circuit 3 ADG732 1 5 na max channel on leakage i d , i s (on) 0.05 na typ v s = v d = 1 v or 3 v; adg726 0.5 2.5 na max test circuit 4 ADG732 1 5 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.7 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.5 a max c in , digital input capacitance 5 pf typ dynamic characteristics 2 t transition 34 ns typ r l = 300 , c l = 35 pf; test circuit 5 52 62 ns max v s1 = 2 v/0 v, v s32 = 0 v/2 v break-before-make time delay, t d 26 ns typ r l = 300 , c l = 35 pf; 1 ns min v s = 2 v; test circuit 6 t on ( wr , cs )29 ns typ v s = 2 v; test circuit 7 43 52 ns max r l = 300 , c l = 35 pf; t off ( wr , cs )26 ns typ v s = 2 v; test circuit 7 38 42 ns max r l = 300 , c l = 35 pf; t on ( en , wr )33 ns typ r l = 300 , c l = 35 pf; 48 55 ns max v s = 3 v; test circuit 8 t off ( en )19 ns typ r l = 300 , c l = 35 pf; 25 28 ns max v s = 2 v; test circuit 8 charge injection 1 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf; test circuit 9 off isolation e72 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 10 channel-to-channel crosstalk e72 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 11 e3 db bandwidth r l = 50 , c l = 5 pf; test circuit 12 adg726 34 mhz typ ADG732 18 mhz typ c s (off) 13 pf typ f = 1 mhz c d (off) adg726 170 pf typ f = 1 mhz ADG732 340 pf typ f = 1 mhz c d , c s (on) adg726 175 pf typ f = 1 mhz ADG732 350 pf typ f = 1 mhz power requirements v dd = 3.3 v i dd 5 a typ digital inputs = 0 v or 3.3 v 10 a max notes 1 temperature ranges are as follows: b version: e40 c to +85 c. 2 guaranteed by design; not subject to production test. specifications subject to change without notice. specifications 1 (v dd = 3 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.)
rev. 0 b version ?0 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on )4 ? typ v s = v ss to v dd , i ds = 10 ma; 5.5 6 ? max test circuit 1 on resistance match between 0.3 ? typ v s = v ss to v dd , i ds = 10 ma channels ( ? r on ) 0.8 ? max on resistance flatness (r flat(on) ) 0.5 ? typ v s = v ss to v dd , i ds = 10 ma 1 ? max leakage currents v dd = +2.75 v, v ss = ?.75 v source off leakage i s (off) 0.01 na typ v s = +2.25 v/?.25 v, v d = ?.25 v/+2.25 v; 0.25 0.5 na max test circuit 2 drain off leakage i d (off) 0.05 na max v s = +2.25 v/?.25 v, v d = ?.25 v/+2.25 v; adg726 0.5 2.5 na max test circuit 3 ADG732 1 5 na max channel on leakage i d , i s (on) 0.05 na typ v s = v d = +2.25 v/?.25 v; adg726 0.5 2.5 na max test circuit 4 ADG732 1 5 na max digital inputs input high voltage, v inh 1.7 v min input low voltage, v inl 0.7 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.5 a max c in , digital input capacitance 5 pf typ dynamic characteristics 2 t transition 33 ns typ r l = 300 , c l = 35 pf; test circuit 5 45 51 ns max v s1 = 1.5 v/0 v, v s32 = 0 v/1.5 v break-before-make time delay, t d 15 ns typ r l = 300 , c l = 35 pf; 1 ns min v s = 1.5 v; test circuit 6 t on ( cs , wr ) 21 ns typ v s = 1.5 v; test circuit 7 30 37 ns max r l = 300 , c l = 35 pf; t off ( cs , wr ) 20 ns typ v s = 1.5 v; test circuit 7 29 35 ns max r l = 300 , c l = 35 pf; t on ( en , wr ) 26 ns typ r l = 300 , c l = 35 pf; 37 ns max v s = 1.5 v; test circuit 8 t off ( en ) 18 ns typ r l = 300 , c l = 35 pf; 26 29 ns max v s = 1.5 v; test circuit 8 charge injection 1 pc typ v s = 0 v, r s = 0 , c l = 1 nf; test circuit 9 off isolation ?2 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 10 channel-to-channel crosstalk ?2 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 11 ? db bandwidth r l = 50 , c l = 5 pf; test circuit 12 adg726 34 mhz typ ADG732 18 mhz typ c s (off) 13 pf typ c d (off) adg726 137 pf typ f = 1 mhz ADG732 275 pf typ f = 1 mhz c d , c s (on) adg726 150 pf typ f = 1 mhz ADG732 300 pf typ f = 1 mhz power requirements i dd 10 a typ v dd = +2.75 v 20 a max digital inputs = 0 v or +2.75 v i ss 10 a typ v ss = ?.75 v 20 a max digital inputs = 0 v or +2.75 v notes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 guaranteed by design; not subject to production test. specifications subject to change without notice. ? adg726/ADG732 specifications 1 (v dd = +2.5 v 10%, v ss = ?.5 v 10%, gnd = 0 v, unless otherwise noted.) dual supply
rev. 0 e5e adg726/ADG732 timing characteristics 1, 2, 3 parameter limit at t min , t max unit conditions/comments t 1 0 ns min cs to wr setup time t 2 0 ns min cs to wr hold time t 3 10 ns min wr pulsewidth t 4 10 ns min time between wr cycles t 5 5 ns min address, enable setup time t 6 2 ns min address, enable hold time notes 1 see figure 1. 2 all input signals are specified with tr = tf = 1 ns (10% to 90% of v dd ). 3 guaranteed by design and characterization, not production tested. specifications subject to change without notice. t 1 t 2 t 3 t 4 t 5 t 6 cs wr a0, a1, a2, a3, (a4) en figure 1 shows the timing sequence for latching the switch address and enable inputs. the latches are level sensitive; there- fore, while wr is held low, the latches are transparent and the switches respond to changing the address and enable the inputs. input data is latched on the rising edge of wr . the adg726 has two cs inputs. this enables the part to be used either as a dual 16-1 channel multiplexer or a differential 16-channel multiplexer. if a differential output is required, tie csa and csb together.
rev. 0 e6e adg726/ADG732 pin configurations lfcsp and tqfp pin 1 indicator top view ADG732 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 nc = no connect v dd 13 v dd 14 a0 15 a1 16 a2 17 a3 18 a4 19 cs 20 wr 21 en 22 gnd 23 v ss 24 36 s28 35 s27 34 s26 33 s25 32 s24 31 s23 30 s22 29 s21 28 s20 27 s19 26 s18 25 s17 48 s13 47 s14 46 s15 45 s16 44 nc 43 d 42 nc 41 nc 40 s32 39 s31 38 s30 37 s29 1 2 3 4 5 6 7 8 9 10 11 12 pin 1 indicator top view adg726 1 s12a 2 s11a 3 s10a 4 s9a 5 s8a 6 s7a 7 s6a 8 s5a 9 s4a 10 s3a 11 s2a 12 s1a nc = no connect v dd 13 v dd 14 a0 15 a1 16 a2 17 a3 18 csa 19 csb 20 wr 21 en 22 gnd 23 v ss 24 36 s12b 35 s11b 34 s10b 33 s9b 32 s8b 31 s7b 30 s6b 29 s5b 28 s4b 27 s3b 26 s2b 25 s1b 48 s13a 47 s14a 46 s15a 45 s16a 44 nc 43 da 42 nc 41 db 40 s16b 39 s15b 38 s14b 37 s13b absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ? v analog inputs 2 . . . . . . . . . . . . . . v ss ?0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 2 . . . . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 30 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . ?0 c to +85 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg726/ADG732 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c thermal impedence (four-layer board) 48-lead lfcsp . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 c/w 48-lead tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.6 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . . 300 c ir reflow, peak temperature (<20 sec) . . . . . . . . . . . . 235 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at a, en , wr , cs , s, or d will be clamped by internal diodes. current should be limited to the maximum ratings given. warning! esd sensitive device ordering guide model temperature range package description package option adg726bcp ?0 c to +85 cc hip scale package (lpcsp) cp-48 adg726bsu ?0 c to +85 ct hin quad flatpack (tqfp) su-48 ADG732bcp ?0 c to +85 cc hip scale package (lpcsp) cp-48 ADG732bsu ?0 c to +85 ct hin quad flatpack (tqfp) su-48
rev. 0 e7e adg726/ADG732 table ii. ADG732 truth table a4 a3 a2 a1 a0 en cs wr switch condition x xxx xx 1 l->h retains previous switch condition x xxx xx 1x no change in switch condition x xxx x 100 none 00000000 1 00001000 2 00010000 3 00011000 4 00100000 5 00101000 6 00110000 7 00111000 8 01000000 9 01001000 10 01010000 11 01011000 12 01100000 13 01101000 14 01110000 15 01111000 16 10000000 17 10001000 18 10010000 19 10011000 20 10100000 21 10101000 22 10110000 23 10111000 24 11000000 25 11001000 26 11010000 27 11011000 28 11100000 29 11101000 30 11110000 31 11111000 32 x = don? care table i. adg726 truth table a3 a2 a1 a0 en csa csb wr on switch x xxx x 11 l->h retains previous switch condi tion x xxx x 11x no change in switch condition x xxx 1 000 none 00000000 s1a da, s1b?b 00010000 s2a da, s2b?b 00100000 s3a da, s3b?b 00110000 s4a da, s4b?b 01000000 s5a da, s5b?b 01010000 s6a da, s6b?b 01100000 s7a da, s7b?b 01110000 s8a da, s8b?b 10000000 s9a da, s9b?b 1 001 0 000 s10a?a, s10b?b 1 010 0 000 s11a?a, s11b?b 1 011 0 000 s12a?a, s12b?b 1 100 0 000 s13a?a, s13b?b 1 101 0 000 s14a?a, s14b?b 1 110 0 000 s15a?a, s15b?b 1 111 0 000 s16a?a, s16b?b x = don? care
rev. 0 e8e adg726/ADG732 terminology v dd most positive power supply potential v ss most negative power supply in a dual-supply application. in single-supply applications, connect to gnd. i dd positive supply current i ss negative supply current gnd ground (0 v) reference s source terminal. may be an input or output. dd rain terminal. may be an input or output. in logic control input v d (v s )a nalog voltage on terminals d and s r on ohmic resistance between d and s ? r on on resistance match between any two channels, i.e., r on max ?r on min r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch off i d (off) drain leakage current with the switch off i d , i s (on) channel leakage current with the switch on v inl maximum input voltage for logic ? v inh minimum input voltage for logic ? i inl (i inh ) input current of the digital input c s (off) off switch source capacitance. measured with reference to ground. c d (off) off switch drain capacitance. measured with reference to ground. c d ,c s (on) on switch capacitance. measured with reference to ground. c in digital input capacitance t transition delay time measured between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another t on ( en )d elay time between the 50% and 90% points of the en digital input and the switch on condition t off ( en )d elay time between the 50% and 90% points of the en digital input and the switch off condition t open off time measured between the 80% points of both switches when switching from one address state to another charge a measure of the glitch impulse transferred from the digital input to the analog output during switching injection off isolation a measure of unwanted signal coupling through an off switch crosstalk a measure of unwanted signal coupling from one channel to another as a result of parasitic capacitance on response the frequency response of the on switch insertion the loss due to the on resistance of the switch loss
rev. 0 e9e v d , v s ?v 8 0 5.5 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1 2 3 4 5 6 7 v dd = 2.7v v dd = 3.0v v dd = 4.5v resistance ? v dd = 3.3v v dd = 5v v dd = 5.5v t a = +25 c v ss = 0v tpc 1. on resistance vs. v d (v s ), single supply v d , v s ?v 8 0 0 1 2 3 4 5 6 7 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 +85 c ?0 c resistance ? +25 c v ss = 0v tpc 4. on resistance vs. v d (v s ), single supply v d , v s ?v q inj ?pc 25 ?5 ? ? 5 ? 01234 20 5 0 ? ?0 15 10 t a = +25 c tpc 7. ADG732 charge injection vs. source voltage v d , v s ?v 8 ?.75 0 1 2 3 4 5 6 7 ?.75 ?.75 0.25 1.25 2.25 v dd = +2.25v v ss = ?.25v t a = +25 c v dd = +2.5v v ss = ?.5v v dd = +2.75v v ss = ?.75v resistance ? v d , v s ?v 8 ?.5 0 1 2 3 4 5 6 7 ?.0 ?.5 ?.0 ?.5 0 0.5 1.0 1.5 2.0 2.5 +85 c ?0 c +25 c resistance ? temperature ? c ?0 ?0 80 0204 060 time ?ns 45 40 0 20 15 10 5 35 25 30 v ss = 0v t on t off v dd = 3v v dd = 5v v dd = 5v v dd = 3v tpc 8. t on /t off times vs. temperature v d , v s ?v 8 0 0 1 2 3 4 5 6 7 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 +85 c ?0 c v ss = 0v resistance ? +25 c tpc 3. on resistance vs. v d (v s ) for different temperatures, single supply temperature ? c 0.5 5 ?.5 15 85 25 35 45 55 65 75 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 v dd = 5v v ss = 0v current na tpc 6. leakage currents vs. temperature v dd ?v 01 6 2345 logic threshold voltage ?v 1.8 1.6 0 0.8 0.6 0.4 0.2 1.4 1.0 1.2 t a = 25 c fa l l ing rising tpc 9. logic threshold voltage vs. supply voltage t ypical performance characteristics adg726/ADG732
rev. 0 adg726/ADG732 ?0 frequency ?mhz 0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0.03 0.1 1 10 100 ?0 ?0 v dd = 5v t a = 25 c a ttenuation ?db tpc 10. off isolation vs. frequency frequency ?mhz a ttenuation ?db 0.03 0.1 100 110 0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 v dd = 3v, 5v t a = 25 c tpc 11. crosstalk vs. frequency frequency ?mhz 0 ?4 ?2 ?0 ? ? ? ? 0.03 0.1 1 10 100 v dd = 5v t a = 25 c ADG732 adg726 a ttenuation ?db tpc 12. on response vs. frequency i ds v1 sd v s r on = v 1 /i ds test circuit 1. on resistance s1 d v s gnd a v s s2 s32 en logic ? v dd v ss v dd v ss i s (off) v d test circuit 2. i s (off) s1 d v s gnd a v d s2 s32 en logic ? v dd v ss v dd v ss i d (off) test circuit 3. i d (off) d v s gnd a v d s1 s32 en v dd v ss v dd v ss i d (on) logic 0 test circuit 4. i d (on) t est circuits address drive (v in ) 0v 3v v out v s1 v s32 t transition t transition 50% 90% 50% 90% v ss v ss v dd v dd 50 v in a4 a0 ADG732 * s2 thru s31 s1 s32 d en v s1 v out r l 300 c l 35pf cs gnd wr * similar connection for adg726 v s32 test circuit 5. switching time of multiplexer, t transition 3v address drive (v in ) 0v v s v out t open 80% 80% v ss v ss v dd v dd 50 v in a4 a0 ADG732 * s2 thru s31 s1 s32 d en v s v out r l 300 c l 35pf cs gnd wr * similar connection for adg726 test circuit 6. break-before-make delay, t open
rev. 0 e11e adg726/ADG732 t on ( wr ) t off ( wr ) 20% 20% 50% 3v 0v wr switch output v o 0v v s v ss v ss v dd v dd v cs a4 a0 ADG732 * s2 thru s32 s1 d en v out r l 300 c l 35pf gnd * similar connection for adg726 cs wr v wr c wn on , t off ( wr 3v 0v en switch output v o 0v 50% 50% 10% 90% t on ( en ) t off ( en ) v s v ss v ss v dd v dd v en a4 a0 ADG732 * s2 thru s32 s1 d cs v out r l 300 c l 35pf gnd * similar connection for adg726 en wr c e on ( en off ( en 0v 3v v out v out q inj = c l v out logic input (v in ) v ss v ss v dd v dd v in a4 a0 ADG732 * d cs v out c l 1nf gnd * similar connection for adg726 en wr r s v s s test circuit 9. charge injection a4 a0 ADG732 * d gnd similar connection for adg726 en 50 v out r l 50 v s network analyzer v dd v ss 0.1 f 0.1 f 50 s off isolation = 20 log v out v s v dd v ss logic 1 * test circuit 10. off isolation
rev. 0 12 c02765 0 7/02(0) printed in u.s.a. adg726/ADG732 v ss v ss v dd v dd a4 a0 ADG732 * d en gnd * similar connection for adg726 channel-to-channel crosstalk = 20log 10 (v out /v s ) wr s2 s32 50 v out r l 50 v s network analyzer cs s1 50 test circuit 11. channel-to-channel crosstalk a4 a0 ADG732 * d gnd * similar connection for adg726 en 50 v out r l 50 v s network analyzer v dd v ss 0.1 f 0.1 f s v dd v ss insertion loss = 20 log v out with switch v out without switch test circuit 12. bandwidth outline dimensions 48-lead frame chip scale package [lfcsp] (cp-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 4.70 2.25 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.25 ref 0.70 max 0.65 nom 1.00 0.90 0.80 5.50 ref seating plane 0.05 max 0.02 nom coplanarity 0.60 max 0.60 max pin 1 indicator compliant to jedec standards mo-220-vkkd-2 48-lead thin plastic quad flatpack [tqfp] (su-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.5 bsc 7.00 bsc sq 0.27 0.22 0.17 9.00 bsc sq seating plane 7 0 1.05 1.00 0.95 1.20 max 0.75 0.60 0.45 0.20 0.09 0 min 0.15 0.05 coplanarity compliant to jedec standards ms-026bbc

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